| 摘要 |
PURPOSE:To prevent the occurrence of false lock by comparing phases at trailing edges, comparing the phases only when a level of input data is logical 1 and continuing an output of a phase difference till a succeeding extracted clock when the level of the extracted clock is not logical 1 while the level of an input signal is logical 1. CONSTITUTION:Since positive outputs G,C of RS-FF (2), (4) are given to reset inputs of RS-FF (1), (3), the positive outputs of the RS-FF (2), (4) are logical 1 at a leading of an input signal and an output signal of a VCO to release resetting of the RS-FF (1), (3), and signals V,DOWN are generated at a trailing of an input signal and an output of a VCO based on negative outputs F,B of the RS-FF (1), (3) and the signals are kept being outputted till a reset signal I is logical 0. Since the reset signal I results from NANDing positive outputs E, A of the RS-FF (1), (3), the phase comparator are operated for the trailing edge by using the signal I generated when both the input signal and the VCO signal are zero. |
