发明名称 SYNTHESIZER RECEIVER
摘要 PURPOSE:To make it possible to select a channel by setting easily the dividing ratio of the programmable divider of a PLL frequency synthesizer with the constitution simplified by providing a frequency counter counting the oscillation frequency of a variable frequency oscillator. CONSTITUTION:The PLL frequency synthesizer 20 is equipped with reference frequency signal generating method 22, programmable divider, phase comparator 13, and switch 94 which feeds the output of comparator 13 back to the 2nd variable oscillation frequency element of local oscillator 8. In addition, this is provided with the method (composed of switches 94 and 95, resistors 96 and 97, power supply +B, etc.) which cuts off the feedback path of synthesizer 20 at the channel selection time and then supplies a constant voltage to the 2nd variable oscillation frequency element of oscillator 8, frequency counters 44 to 46 which are supplied with signals of a frequency relating to the oscillation frequency of oscillator 8, and latch circuits 50 to 52 which set the dividing ratio of divider 10 of synthesizer 20 corresponding to the frequency read by counters 44 to 46.
申请公布号 JPS54102814(A) 申请公布日期 1979.08.13
申请号 JP19780009137 申请日期 1978.01.30
申请人 SONY CORP 发明人 SOMENO NOBORU
分类号 H03L7/18;H03J5/00;H03J5/02;H03L7/23;H04B1/26;H04B1/28 主分类号 H03L7/18
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