Computer power management systems.

摘要

A power management unit is provided that monitors various portions of a computer system and causes a reduction in the frequencies of the CPU clock signal and the system clock signal during a power conserving state. The power management unit includes a programmable counter for allowing the system designer to vary the length of a wake-up period that occurs in response to an assertion of a timer tick interrupt. An in-service register of an interrupt controller is coupled to the power management unit which thereby allows the power management unit to receive real-time information regarding whether a timer tick interrupt is currently being serviced by the microprocessor. When a timer tick status bit of the in-service register is set, the power management unit causes the CPU clock signal and the system clock signal to be driven at maximum frequencies. When the timer tick status bit clears, the programmable counter begins counting. The power management unit advantageously causes the clock signals to be driven at the maximum frequencies for a length of time as determined by the programmable counter, and subsequently causes the clock signals to be driven at the reduced power-conserving frequencies when the counter expires. By accurately controlling the wake-up period of the computer system in this manner, a reduction in the overall power consumption of the computer system can be attained.