SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

摘要

This method reduces pulse delay between memory cell region and periphery in a high integration semiconductor device of CMOS structure which has more than twin wells, to simplify the etching process of following processes, and prevents the short circuit of wires in forming metal pattern. The method comprises the step of: depositing sequentially oxide layer and nitride layer on the semiconductor substrate; taking a phothoresist on the nitride layer; taking the photoresist out from the p-type well region to be formed by photolithography process; ion implanting p-type dopant into the region with removed photoresist; forming oxide layer onto the surface of the p-type well; ion implanting n-type dopant; and forming the n-type well by drive-in process.