Semiconductor memory apparatus formed of a plurality of small memory cells arrays having columns of memory cells connected to column selection word lines through selection transistors

摘要

A memory cell array is divided into a plurality of row sections in a column direction, and one main bit line is arranged between two adjacent columns. One pair of sub bit lines are arranged for each column of the row sections, and the pair of sub bit lines are connected to main bit lines exclusively of sub bit lines which are adjacent to the pair of sub bit lines in columns on both sides of the pair of bit lines. For this reason, the pitch of main bit lines can be set to be almost twice that of conventional main bit lines. Therefore, the time required for the charging/discharging operations of the bit lines can be shortened to increase the operating speed, reliability can be improved, and a yield can be increased.