发明名称 |
Transparent flip-flop |
摘要 |
An apparatus for a transparent master/slave flip-flop logic circuit including a single line connected to the transparency input of the logic macro so that when the line is active input data will pass through the flip-flop, unless the scan signal is also active, in which case the flip-flop will return to a clocked (latching) status.
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申请公布号 |
US5416362(A) |
申请公布日期 |
1995.05.16 |
申请号 |
US19930119957 |
申请日期 |
1993.09.10 |
申请人 |
UNISYS CORPORATION |
发明人 |
BYERS, LARRY L.;ARRAUT, FERNANDO W.;SEPPA, DALE K. |
分类号 |
H03K3/037;(IPC1-7):H03K3/037;H03K3/289 |
主分类号 |
H03K3/037 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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