| 发明名称 |
IMAGE PROCESSOR |
| 摘要 |
The codec processor includes an SRAM that holds a reference image read from an image storage, and a motion search unit that performs motion search on the basis of a reference image held in the SRAM to generate a prediction block for a target block in an input image. The SRAM holds a reference image having a horizontally equivalent number of pixels to a horizontal number of pixels of the input image and a number of pixels vertically larger than or equal to a vertical motion search range. |
| 申请公布号 |
US2015172706(A1) |
申请公布日期 |
2015.06.18 |
| 申请号 |
US201414572887 |
申请日期 |
2014.12.17 |
| 申请人 |
MegaChips Corporation |
发明人 |
OKAMOTO Akira |
| 分类号 |
H04N19/57;H04N19/593;H04N19/176;H04N19/139;H04N19/172 |
主分类号 |
H04N19/57 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An image processor comprising:
a codec processor configured to code an input image; and an image storage accessible by the codec processor, the codec processor including a reference image holding unit being configured to hold a reference image from the image storage; and a motion search unit configured to perform motion search based on a reference image in the reference image holding unit to generate a prediction block for a target block in the input image, the reference image holding unit being configured to hold a reference image having a horizontally equivalent number of pixels to a horizontal number of pixels of the input image and a number of pixels vertically larger than or equal to a vertical motion search range. |
| 地址 |
Osaka-shi JP |
