发明名称 |
NAPNOP CIRCUIT FOR CONSERVING POWER IN COMPUTER SYSTEMS |
摘要 |
A NAPNOP circuit for decreasing energy consumption of all or a portion of a microprocessor based system which includes a delay circuit for inhibiting or slowing the output of the system clock pulses for a variable length of time equal to a multiple of N clock pulses where N is a positive integer. The NAPNOP circuit has an input element for inputting a STARTNAP signal which begins a nap period during which the system clock pulses are inhibited or slowed, a clock input device for providing a plurality of selectable clock pulses as inputs to the delay circuit for controlling the operation of the computer system, and a gate element for terminating the nap period.
|
申请公布号 |
CA2110068(A1) |
申请公布日期 |
1995.05.16 |
申请号 |
CA19932110068 |
申请日期 |
1993.11.26 |
申请人 |
KENNY, JOHN D.;MA, MIN S. |
发明人 |
KENNY, JOHN D.;MA, MIN S. |
分类号 |
G06F1/04;G06F1/06;G06F1/32;G06F9/30;G06F9/38;(IPC1-7):G06F1/32 |
主分类号 |
G06F1/04 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|