| 摘要 |
The circuit prevents the unnecessary operation of sensor amplifier by adjustment of memory output signal. The circuit includes the 1st and 2nd logic gates(G1 and G2) which connect the BHE signal(BHE) and input address(AX1) to the 2nd logic gate(G2), the 3rd logic gate(G3) which connects the chip enable signal(CE), the 4th logic gate(G4) which connects to the output signal of the 2nd logic gate(G2), the 5th and 7th logic gates(G5 and G7) which connect to the 9th logic gate(G9), the 6th and 8th logic gates(G6 and G8) which have the 10th logic gate(G10), and the sensor amplifier group 2 (32).
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