| 摘要 |
PURPOSE:To use only one detection circuit for early/late in the early/late type of synchronizing detection circuit and to attain synchronizing even when clock frequencies of PN codes for transmission reception are deviated. CONSTITUTION:An SS reception signal is divided and distributed into detection circuit blocks M, S and inversely spread by a PN code from PN code generators 56, 57. A quantized value obtained by the processing in the detection circuit blocks M,S is stored in memory 45-48 and a comparator 49 compares quantized values in the memory 45-47 and a comparator 50 compares start bits of both the PN code. The deviation of the result of both comparison is counted by an up-down counter 52, the count is fed to a VCO 54 to control the clock frequency in PN code generators 56, 57. A selector 60 selects an inverse spread PN code or its delayed code. |
