| 摘要 |
PURPOSE:To provide a semiconductor integrated circuit which can easily automate the generation of a test pattern for testing a comparator for comparing the output of a partial logic circuit in the same structure being incorporated in the semiconductor integrated circuit. CONSTITUTION:When testing a comparator 104, '1' is input to an external input 113 and scan flip-flops 120 and 121 are switched to a scanning mode. The test data of the comparator 104 are input from an external input 105, are set to a terminal Q of the scan flip-flops 120 and 121 by scaning, and are fed to the comparator 104. The test result of the comparator 104 is observed with an external output 115. Therefore, it is not necessary to consider the operation of RAMs 102 and 103 for testing the comparator 104, thus achieving automation by an automatic test pattern generation tool. |
