Apparatus and method for trellis decoder.

摘要

A digital data processing apparatus capable of reducing a circuit scale without deteriorating error-correcting capability, and capable of reducing the bit number of a branch metric calculating circuit. The apparatus includes: a region determining portion (13) which determines an optimal bit number corresponding to the number of representative symbol groups; a delaying portion which delays an output from the region determining portion (15) for as long as a coded bit is decoded by a Viterbi decoding portion (11); and a decoding portion (17) which inputs and decodes an output from the delaying portion and a coded bit that is decoded by the Viterbi decoding portion so as to be decoded, and which outputs the uncoded bit. <IMAGE>