The invention concerns a circuit (SPSA) comprising a processing unit (VE) with an electrically erasable and programmable read-only memory (EEPROM), a classification unit (KE) and an interface unit (EIF) for the read-only memory. The processing unit (VE) reads out of the read-only memory (EEPROM) instructions and/or data which are automatically programmed by the classification unit (KE) and interface unit (EIF) as a function of processing-unit inputs (E) and/or internally generated values (ED, S) and/or processing-unit outputs (A). The processing unit may consist of a fuzzy-logic controller or an ordinary microprocessor. The circuit proposed has the particular advantage that it automatically adapts to differences in the structure of the system with which it is associated (type versatility) and to changes in the system with time (due to ageing or wear, for instance), and the circuit thus has a wider range of applications and ensures optimum performance for a longer period of time.
