发明名称 ERASE VERIFYING METHOD FOR VIRTUAL GROUND TYPE FLASH MEMORY AND VIRTUAL GROUND TYPE FLASH MEMORY
摘要 <p>PURPOSE:To shorten a time required for erase verification by performing erase verification of plural memory elements at the same time, in a virtual ground type flash memory. CONSTITUTION:In a flash memory cell array MC having array constitution of a virtual ground type, at the time of verifying erase, a column line B5 of one end in the array MC is connected to a sense circuit amplifier through a N type MOSFETMV1, a column line B1 of the other end is connected to ground through a N type MOSFETMS1 and MS4, and a row line W1 is selected. Thereby, a current flowing from the column line B5 to the column line B1 through memory elements M11-M14 connected to the row line W1 is tested by the sense circuit amplifier, and erase verification for the memory elements M11-M14 is simultaneously performed.</p>
申请公布号 JPH07111091(A) 申请公布日期 1995.04.25
申请号 JP19930253013 申请日期 1993.10.08
申请人 NEC CORP 发明人 JINBO TOSHIKATSU
分类号 G11C17/00;G11C16/02;G11C16/04;G11C16/34;(IPC1-7):G11C16/06 主分类号 G11C17/00
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