发明名称 |
Memory integrated circuit with protection against disturbances |
摘要 |
Disclosed is an integrated circuit memory comprising at least one column of memory cells parallel connected with one another and connected to at least one bit line, each memory cell being connected to a bit line by at least one access transistor, wherein said memory contains a protection transistor that is connected to the bit line and controlled so as to be made conductive so as to limit the voltage drop on the bit line, during the stages of the reading of the memory, when this drop in voltage goes beyond a threshold having a value smaller than a value that prompts the writing of an information element in a memory cell. |
申请公布号 |
US5410506(A) |
申请公布日期 |
1995.04.25 |
申请号 |
US19940274142 |
申请日期 |
1994.07.14 |
申请人 |
THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES |
发明人 |
FERRANT, RICHARD;FEL, BRUNO |
分类号 |
G06F11/00;G11C7/12;G11C11/419;(IPC1-7):G11C7/00 |
主分类号 |
G06F11/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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