| 发明名称 |
Digital phase-locked loop circuit |
| 摘要 |
A digital phase locked loop which incorporates a phase comparator which produces a phase deviation signal having a sinusoidal phase comparison characteristic rather than a sawtooth phase comparison characteristic in order to avoid aliases.
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| 申请公布号 |
US5410573(A) |
申请公布日期 |
1995.04.25 |
| 申请号 |
US19930149005 |
申请日期 |
1993.11.08 |
| 申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
TAGA, NOBORU;ISHIKAWA, TATSUYA;KOMATSU, SUSUMU |
| 分类号 |
H03L7/085;H03L7/087;H04L27/00;H04L27/233;(IPC1-7):H03D3/24 |
主分类号 |
H03L7/085 |
| 代理机构 |
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