发明名称 VARIABLE LENGTH CODING DECODER
摘要 A control circuit controls the decoding operation of the decoding circuit. An information type buffering circuit delivers type signals indicating whether frames, slices and macro blocks are full information or difference information, and delivers horizontal/vertical motion vector information. An extra run level generating circuit produces data corresponding to a shortage of data, based on a run length code decoding signal delivered from the decoding circuit. A multiplexing circuit composes an extra run level signal from the extra run level generating circuit, decoded luminance information and decoded colour information together. A data buffering circuit is provided for buffering luminance signals and colour signal. A coefficient generating circuit detects discrete cosine transform (DCT) coefficients from the luminance signals and colour signals and delivers the detected DCT coefficients.
申请公布号 KR950004129(B1) 申请公布日期 1995.04.25
申请号 KR19920008454 申请日期 1992.05.19
申请人 GOLDSTAR CO., LTD. 发明人 LEE, HUNG - SUN
分类号 H03M7/42;H04N7/50;(IPC1-7):H04N7/30 主分类号 H03M7/42
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