| 摘要 |
PURPOSE:To provide a reset system which can evade such a case where a receiving circuit becomes defective and unable to perform a normal operation due to a fast clock signal that is produced by the noises in a simultaneous transmission state of both clock and data signals. CONSTITUTION:A data detecting part 102 detects the burst data start timing among the received signals 101. A reset part 103 inputs the burst data and outputs a reset signal in the burst data start timing. A 1st delay part 104 delays the burst data by a 1st prescribed time, and a receiving path receiver the output of the part 104 as the delay data. A 2nd delay part 108 outputs a delay timing signal when a 2nd prescribed time passed from the burst data start timing. A control part 106 is reset by a reset signal and controls the operation of the receiving part in response to the delay timing signal. The 1st and 2nd prescribed times are decided by the time needed for reset of the part 106. |
