| 摘要 |
A branch processing unit (BPU) is used, in an exemplary embodiment, in a superscalar, superpipelined microprocessor compatible with the x86 instruction set architecture. The BPU (140) predicts the direction of branches, and provides target addresses for predicted taken branches and unconditional change of flow (UCOF) instructions (jumps, calls, returns). The BPU includes a target cache (110) for storing target addresses for UCOFs and predicted taken branches -- a history cache (120) stores history information for branches predicted not taken. A return address stack (130) stores target addresses for returns associated with calls stored in the target cache, while a far target cache (140) stores limits and mode bits for far targets stored in the target cache. Resolution logic (150) monitors branch execution, resolving branch predictions and repairing the execution pipeline in the case of mispredictions. The BPU is accessed at prefetch time with the prefetch address. For accesses that hit in the BPU, the target address is supplied to prefetcher (35), which begins prefetching at the predicted target address, shifting the code stream in one clock as it enters the prefetch buffer (30). A branch is allocated into the resolution logic when it issues (from the ID2 pipe stage) -- a branch will issue only if the number of outstanding (unresolved) branches (or floating point instructions) is three or less. For issued branches, the prefetcher prefetches in both the predicted and not-predicted direction -- NP prefetch registers (164) store prefetched instruction bytes in the not-predicted direction such that, in the case of a branch misprediction, the contents of the corresponding NP prefetch buffer are transferred to the prefetch buffer (162) to initiate repair. For calls, return target addresses are pushed onto the return address stack either (a) when a call hits in the target cache during prefetch, or (b) for a previously undetected call, when the call is decoded. For far targets, the far target cache stores limits and modes, and is accessed by indirection bits stored with a far target in the target cache <IMAGE> |
