Wiring topology for transfer of electrical signals.

摘要

The wiring topology includes an input impedance network having a first impedance, a first branch network connected to the input impedance network contg two portions having an impedance greater than the input network. A second branch network is provided for attaching to corresp devices and is connected to at least one of the portions of the first branch network contg fourth portions with an impedance grater than each of the two portions. In the wiring topology the second branch network is non-terminated while device used are of a semiconductor type. The line impedances transfer address, control or clock signals for a memory device.