| 摘要 |
The system and method disclosed herein relates to digital halftoning where a threshold array is used to control individual pixels in a halftone cell. The threshold array is replicated to tile the entire device space so that each pixel in device space is mapped to a particular location in the threshold array. By tiling the threshold array with overlap, the size of the overall threshold array is reduced. A CPU interface couples a FIFO buffer, registers, and RAM to a CPU for receiving pixel data, control signals and other values, respectively. An engine control unit is coupled to control a video processing unit and an output device for producing halftone images with a halftone matrix of reduced size. The engine control unit controls threshold logic that applies the threshold matrix to the pixel data to produce the data stream sent to the output device. The method of the present invention preferably comprises the steps of: defining a halftone cell and a minimal threshold array; mapping the threshold array over device space; determining a row and a column in the threshold array for the previous pixel of the image that has been rendered to device space; determining whether the next pixel is vertically adjacent or horizontally adjacent to the pixel that was previously mapped to device space; determining whether the next pixel is within the threshold array used for the previous pixel; and adjusting the mapping to account for overlapping threshold arrays if the next pixel is not within the threshold array used for the previous pixel. |
