PROCESS INDEPENDENT DESIGN FOR GATE ARRAY DEVICES

摘要

A unique gate array cell and ASIC library development methodology is taught which require no new simulations or new place and route to port a given device design to a same generation process technologies which are available from different vendors. This methodology makes use of the minimum design rules from different vendors without reroute of the physical database. This methodology equalizes the functionality and timing characteristics of the macrocell library on a plurality of alternate sources.