| 摘要 |
PURPOSE:To prevent an operation state from being deviated from design due to the drop of the drain instantaneous voltage of an FET to be an amplification element in an F class power amplifier to a level less than knee voltage. CONSTITUTION:A serial circuit consisting of a diode 8 and a capacitor 7 is connected to loads 4 to 6 for an FET 1 in parallel and bias (VD-VK) is applied to the diode 8. When the absolute value of the output instantaneous voltage of the FET 1 exceeds the bias (VD-VK), the diode 8 is turned on, an AC ground state is set up and the peak of the instantaneous voltage is limited to the (VD-VK). Thereby the peak value of drain voltage is limited, so that the reduction of the drain current is suppressed, the distortion of the drain current is removed and ideal operation can be attained. |
