发明名称 SEQUENTIAL ARITHMETIC CIRCUIT
摘要 PURPOSE:To prevent an error due to electric charge charging and to prevent an error due to initialization by specifying the opening/ closure timing of an initialization switch. CONSTITUTION:Respective sample holding circuits H1-H10 are each constituted by connecting an input-side switch SW2, a capacitance e11, a 1st-stage amplifier AMP1, a capacitance C21, and a 2nd-stage amplifier AMP2 in series. The input and output of the AMPs 1 and 2 are connected by feedback capacitances C12 and C22 and also connected by 1st and 2nd initialization switches SW3 and SW6 so that they can be opened and closed; and the amplifier of the arithmetic circuit which processes the output is connected by a 3rd initialization switch(SW 7) so that it can be opened and closed. Then the 2nd or 3rd initialization switch SW6 (SW7) is closed a sufficient time after the 1st initialization switch SW3 is opened, and the 1st initialization switch SW3 is closed after the 2nd or 3rd initialization switch SW6 (SW7) is opened.
申请公布号 JPH0793441(A) 申请公布日期 1995.04.07
申请号 JP19930256385 申请日期 1993.09.20
申请人 TAKAYAMA:KK 发明人 KOTOBUKI KOKURIYOU;TAKATORI SUNAO;YAMAMOTO MAKOTO;OOSAWA CHIKASHI;URUSHIBATA AKIRA
分类号 G06G7/12;G06G7/14;G06G7/16;G11C27/02;(IPC1-7):G06G7/12 主分类号 G06G7/12
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