发明名称 METHOD OF ASSEMBLING SUBROUTINES
摘要 The invention relates to data processing systems and particularly to intercommunication arrangements for use in multiprocessor systems of the distributed algorithm type. In such systems each programme routine is provided with at least one input data area (input well) and at least one output data area (output well) each routine being arranged to process a block of data (input data packet) in an input well and to produce a processed block of data (output data packet) in an output well. Additionally common data areas (queues) are provided arranged to temporarily store related data packets on a first-in first-out basis. The processor input-output instructions are used to provide automatically activated arrangements to transfer a data packet from a relevant queue to a particular routine related input well immediately prior to the commencement of a programme routine and to transfer the processed data pocket to a relevent queue from an output well immediately after the completion of the routine regardless of the relative locations of the co-operating wells and queues. The provision of input and output wells allows for the use of self-contained programme-routines while the provision of queues between routines allows for the asynchronous performance of those routines.
申请公布号 US3657736(A) 申请公布日期 1972.04.18
申请号 USD3657736 申请日期 1969.12.22
申请人 PLESSEY BTR LTD. 发明人 ROGER J. BOOM;JOHN M. COTTON;MARTIN J. GOODIER;DAVID C. COSSERAT
分类号 G06F9/22;G06F9/40;G06F9/46;G06F9/48;H04Q3/545;(IPC1-7):G06F9/00 主分类号 G06F9/22
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