发明名称 SEMICONDUCTOR MEMORY
摘要 PURPOSE:To improve relieving probability by providing a spare memory cell according to a block, and switching selectively a defective generating block to a spare memory cell by row and column selecting means, in a memory cell array divided into plural blocks. CONSTITUTION:Defects of each block of divided memory cell array are examined, it is selected whether 4K refresh can be performed or not in a DRAM of 64M bits, while if a defective column exists in selected two blocks, an activated block is changed and not made to be selected at the same time. Further, a block in which 8K refresh can be performed is selected among blocks in which 4K refresh can be performed and it is relieved. At the time, a row address signal 12R is generated from an input address signal in an address input switching circuit, and outputs of NOR gates 38, 39 are supplied to an address allocation switching circuit as a H level or L level in accordance with refresh of 4K or 8K and switching is performed. Thereby, the relieving probability of an address of a defective column can be improved.
申请公布号 JPH0785690(A) 申请公布日期 1995.03.31
申请号 JP19930227419 申请日期 1993.09.13
申请人 TOSHIBA CORP 发明人 OSAWA TAKASHI
分类号 G11C11/401;G11C11/406;G11C11/408;G11C29/00;G11C29/04 主分类号 G11C11/401
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