| 摘要 |
The circuit detects the failure of outpit ports by testing the X1 type DRAM under the condition attateched in PC. The circuit comprises a performance board(1), a probe card(2), and DUT(3). A mode selection relay(16) generates a write enable signal(WE) according to PPS signal to setect one between isolated I/O lines and common I/O lines. A NMOS transistor(18) conducts a contact control between a data input line(Din) and a data output line(Dout) for common I/O lines according to the output of the mode selection relay(16).
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