发明名称 |
Parity inversion test system |
摘要 |
A parity inversion test system includes an interface part having an input side coupled to a N-bit data line and an output side coupled to a M-bit data line, where N<M, an output coupling part for coupling at least a part of a data output from the output side of the interface part to the data output from the output side of the interface part in a test mode so as to output a M-bit data, a parity generating part for generating a parity data with respect to the M-bit data output to the M-bit data line via the output coupling part based on the M-bit data, and a parity inversion bit specifying part for specifying arbitrary bits of the M-bit data output to the M-bit data line which are to be inverted when generating the parity data in the parity generating part.
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申请公布号 |
US5402430(A) |
申请公布日期 |
1995.03.28 |
申请号 |
US19920955826 |
申请日期 |
1992.10.02 |
申请人 |
FUJITSU LIMITED |
发明人 |
ASAI, MASAO;SHIBATA, YUJI;OKAZAKI, MAKOTO |
分类号 |
G06F11/10;G06F11/08;G06F11/267;(IPC1-7):G01R31/00 |
主分类号 |
G06F11/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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