Semiconductor permanent memory device

摘要

A NAND-cell-type EEPROM comprises a memory cell array, in which electrically overwritable memory cells are arranged in matrix form and a multiplicity of data circuits (L/S circuits in a main-bit-line control circuit) for the storage of data for controlling the state of a reading operation of data in memory cells in the memory-cell array. A bit-line voltage is controlled according to the writing data in the data circuit after the loading of the data. Since the voltage on the bit line changes when there is a current leakage, a faulty writing operation caused by a defective bit line with a current leakage can be prevented by setting the data in the data circuit which specify that the bit-line voltage has been sampled after the loading of the data. This makes it possible to carry out the data loading a short time after the writing mode is switched on, and creates an easy-to-use NAND-cell-type EEPROM with a high relief efficiency for defective bit lines. <IMAGE>