| 摘要 |
A transistor amplifier having a main amplifier exhibiting a substantially doubled fT characteristic and having error cancellation circuitry, wherein the standing current of the error cancellation circuitry is reused in powering the main amplifier. The main amplifier comprises an outer differential pair of transistors and an inner differential pair of transistors, each differential pair having an inverting side and a non-inverting side. The collectors of the transistors of the non-inverting side of the differential pairs are connected, respectively, at a first current summing node. The collectors of the transistors of the inverting side of the differential pairs are connected, respectively, at a second current summing node. The fT doubler transistor amplifier also employs level shifter stages to shift the input signals for application to the error cancellation circuitry, the level shift being an amount predetermined to substantially center the error cancellation circuitry in its dynamic range of operation. The fT doubler transistor amplifier also provides current sources which contribute to powering the main amplifier and which source current in amounts predetermined to control positive feedback from the main amplifier to the error cancellation circuitry so as to enhance accurate cancellation of errors.
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