| 摘要 |
A detection unit (46) detects an input pattern stored in an input pattern storage (45) corresponding to a signal inputted to a random logic unit (2). An expected pattern responsive to the input pattern detected by the detection unit (46) is transmitted from the expected pattern storage (52) to a comparator (6). The comparator (6) compares an output from the random logic unit (2) with the expected pattern, and then an error processing circuit (7) processes the comparison result. The error processing circuit (7) stores the details of the error in an error register (8), and makes the data in the register (8) transmittable through a data bus (34) to the outside of a failure detection circuit (101b). The information concerning the error is processed statistically and the data stored in the input pattern storage (45) and expected pattern storage (52) are properly rewritten, so that an improvement in failure detection ration can be achieved. |
