| 摘要 |
PURPOSE:To assure the specification of a level to generate a failure, making a signal line for instructing the occurrence of a pseudo failure into one line and to improve a reliability by providing a pseudo failure generating control means and a hit level displaying means. CONSTITUTION:For an AND circuit 9 to receive an instruction to generate a pseudo failure by making a signal line 10 into a logical value '1', since an access request stored into a request register 4 is a cache reading request, a signal line 12 is made into the logical value '1' by a decoding circuit 5, and at the time when a comparing and hit deciding circuit 6 detect the hit, and a signal line 13 comes to be the logical value '1', the level of a signal line 14 is made into '1'. Thus, an error detecting circuit 8 mades the level of a signal line 15 into the logical value '1', and causes forcibly a flip-flop 35 for displaying an error to light up. By the displaying contents of flip-flops 30-33, a level is specialized, the bit equivalent to a degrading register 40 is made into the logical value '1', and the output corresponding to the comparing and hit deciding circuit 6 is made invalid. |
