发明名称 |
Offset reduction in a zero-detecting circuit. |
摘要 |
The offset of a zero-crossing detector circuit is virtually eliminated by inverting the inputs of the comparator after a certain delay from a detected zero-crossing while storing the output state assumed pursuant the detection of a zero-crossing for an interval of time longer than said delay but shorter than the minimum interval of time occurring between any two successive zero-crossings of the input signal. <IMAGE> <IMAGE> |
申请公布号 |
EP0643484(A1) |
申请公布日期 |
1995.03.15 |
申请号 |
EP19930830379 |
申请日期 |
1993.09.14 |
申请人 |
STMICROELECTRONICS S.R.L. |
发明人 |
BETTI, GIORGIO;GADDUCCI, PAOLO;MOLONEY DAVID |
分类号 |
H03F1/30;H03F3/45;H03K5/1536;H03K17/13;H03K17/60 |
主分类号 |
H03F1/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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