Semiconductor memory device with data error compensation

摘要

A semiconductor memory device includes signal lines, a decoder for decoding an inputted address to output the decoded result to some of the signal lines, a matrixed memory array, a part of which being pre-specified as a compensated area, read out means for reading out data from memory cells in an area specified in accordance with a decode signal on the some signal line, a detector for detecting that the address is related with the compensated area from the decode signal on the some signal lines, the compensated area being pre-related with the some signal lines, and a fixed data outputting circuit for merging predetermined data into a predetermined part of the data read out from the memory cells in accordance with the detection signal to output the merged data. The fixed data outputting circuit is controlled by a control circuit in response to a merge control signal to output the data read out from the memory cells without the merging operation.