| 摘要 |
PURPOSE:To increase the memory access speed of an IP where a cache is bound to a main storage. CONSTITUTION:The request from the IP passes disributors 21, 22, 31, and 32 to reach queues 23, 24, 33, and 34 or reaches queues 251, 252, 351, and 352 for the purpose of accessing another SC. After the request which reaches queues 23, 24, 33, and 34, WS tags 27 and 37 are retrieved to confirm the storage in a cache WS, and WSs 28 and 38 are accessed. If pertinent data is stored in WSs as the result of retrieval of WS tags 27 and 37, MSs 41 and 42 are accessed for pertinent data. Thus, the private interface is provided between the IP and the SC to eliminate the unnecessary wait time, and data of this interface is generated in the IP and retrieval is performed in parallel with another RAM to eliminate the unnecessary wait time of SC access. |
