发明名称 ADDER
摘要 PURPOSE:To shorten the processing time and to reduce the amount of hardware by determining a positive or negative sign in accordance with the number of positive or negative values of three data in the absolute value form and the value of the last carry. CONSTITUTION:For example, when data A0 and B0 out of three data A0, B0 and C0 of data 1 in the absolute value form are negative and only data C. is positive, an inverting circuit 12 outputs data A, B, and C, where the fixed- point part of only data C0 is inverted to adders 10 and 11. The adder 11 performs addition of A+B+C+1, and the adder 10 performs addition of A+B+C. An inverting circuit 15 takes the addition value of the adder 10 as the input and inverts its value to output the result. A selecting circuit 13 selects the output of the inverting circuit 15 as the one's complement of A+B+C and outputs this output as a fixed-point part addition result 3. A sign calculating circuit 14 outputs the sign part addition result of the negative sign because only data C0 is positive and the last carry is 0.
申请公布号 JPH0764767(A) 申请公布日期 1995.03.10
申请号 JP19930214700 申请日期 1993.08.31
申请人 KOFU NIPPON DENKI KK 发明人 KAWAGUCHI TADAHARU
分类号 G06F7/50;G06F7/38;G06F7/483;G06F7/507;G06F7/509 主分类号 G06F7/50
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