| 摘要 |
The bit line charging and equalizing circuit of a semiconductor memory includes a P-channel transistor parallelly connected to a bit line, a P-channel transistor whose drain and source are connected between the bit line and power voltage terminal, the P-channel transistor pre-charging the bit line, and an N-channel transistor whose source and drain are connected between the bit line and power voltage terminal, the N-channel transistor pre-charging the bit line, thereby making read and write operation fast.
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