| 摘要 |
The memory reset circuit comprises a p-type MOS transistor for preventing pull-up transistors from operating a bit line, the p-type MOS transistor employing an external signal as its gate input signal, and an n-type MOS transistor for applying signals having different levels to data bit lines, the n-type MOS transistor employing the external signal as its gate input signal, thereby reducing chip testing time.
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