发明名称 POWER CONSUMPTION REDUCTION CONTROL METHOD/CIRCUIT FOR BUS CIRCUIT
摘要 PURPOSE:To reduce the power consumption of a bus circuit and then to reduce the power consumption of an electronic equipment by minimizing the sub changing frequency. CONSTITUTION:When a bus control circuit 1 is set in an output state, a switch means 1b connects the output OUT to a bus 2 to activate this bus. In this bus active state, the bus output is held by a latch means 1a. When the bus 2 becomes inactive, the signal level of the bus 2 is fixed at a level set in a bus active state. When the circuits 3a and 3b are set in the output states, the means 1a holds the signals transmitted on the bus 2 from both circuits 3a and 3 and fixes the signal level of the bus 2 at a level set in a bus active state after the bus 2 is set in an inactive state. Furthermore the signal level of the bus 2 can also be fixed with a switch means and a latch circuit provided on the preceding and next stages respectively or by means of a pull-up resistance and a pull-down resistance.
申请公布号 JPH0756660(A) 申请公布日期 1995.03.03
申请号 JP19930201509 申请日期 1993.08.13
申请人 FUJITSU LTD 发明人 WATANABE HIROAKI
分类号 G06F3/00;G06F13/40;H03K19/00;(IPC1-7):G06F3/00 主分类号 G06F3/00
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