| 摘要 |
<p>The invention concerns a phase-locked loop (PLL) system, in particular a PLL system for the generation of the combination frequency for the frequency-conversion stage of an FM receiver. Series-connected to a first PLL circuit with a reference or output signal with a first, low, frequency is a second PLL circuit with a reference or output signal with a second, higher, frequency, the output signal of the first PLL circuit being fed as input to the second PLL circuit. The ratio of the output signal of the first PLL circuit to its reference signal is determined by a first frequency divider which produces, from this output signal, a signal for the phase-comparison switching of the first PLL circuit, whose frequency is decreased by an amount corresponding to the ratio determined by the first frequency divider. The ratio of the output signal of the second PLL circuit to its reference signal is determined by a second frequency divider which produces, from this output signal, a signal for the phase-comparison switching of the second PLL circuit, whose frequency is decreased by an amount corresponding to the ratio determined by the second frequency divider.</p> |
