发明名称 FOURRBIT SQUAREELAW CIRCUIT
摘要 PURPOSE:To make an arithmetic speed high by reducing the number of input terminals of an integrated circuit by constituting a four-bit square-law circuit without using a multiplier. CONSTITUTION:The input consists of four bits A3 to A0, and the output of square- law calculation of eight bits B7 to B0. Here, A0 and B0 are the lowest bits, and A3 and B7 are the highest bits. The lowest bit B0 of the output is equal to the lowest bit A0 of the input. Then, B1 is ''0'' at any time. Bit B2 is AND between NOT of A0 and A1. Bit B3 is AND between A0 and OR-ELSE between A1 and A2. Bit B4 is AND between AO and OR-ELSE between A2 and A3. Bit B5 is AND BETWEEN AO and OR-ELSE between AND between A1 and OR-ELASE between A2 and A3, and AND among three inputs A0, A2 and A3. Bit B6 is AND between AND between A3 and NOT of A2, and AND amng three inputs A1, A2 and A3. Then, B7 is equal to AND between A2 and A3.
申请公布号 JPS54137935(A) 申请公布日期 1979.10.26
申请号 JP19780045266 申请日期 1978.04.19
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 YOKOTA TAKASHI;KIDODE MASATSUGU;SHINODA HIDENORI;ASADA HARUO
分类号 G06F7/552 主分类号 G06F7/552
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