发明名称 Switching matrix with asynchronous transfer mode
摘要 This matrix includes: - N queues (Q0, ..., Q15) at each input (E0, ..., E15), each queue corresponding to one of the outputs of the matrix (S0, ..., S15) - a complete interconnection network (RI) making it possible to link the output of any queue to any output of the matrix; - an arbitration circuit (CLA) controlling this complete interconnection network on the basis of the contents of the queues, so as to transmit one cell at most to each output of the matrix, during each cell period. Application to the production of switching systems for telecommunications in the field of local networks or public networks transmitting data. <IMAGE>
申请公布号 FR2709222(A1) 申请公布日期 1995.02.24
申请号 FR19930010114 申请日期 1993.08.19
申请人 ALCATEL CIT 发明人 HELOU DIDIER
分类号 H04L12/54;H04L12/70;H04L12/933;H04Q11/04;(IPC1-7):H04Q11/04 主分类号 H04L12/54
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