发明名称 MODIFIED WALLACE-TREE ADDER FOR HIGH-SPEED BINARY MULTIPLIER, STRUCTURE AND METHOD
摘要 <p>A carry-save adder for use in a binary multiplier with a reduced number of full adder stages. The carry-save adder is summing columns of binary data and is implemented with a plurality of one-bit (30) and two-bit (60) full adders. The one-bit (30) and two-bit (60) full adders are configured in a plurality of interconnected modified Wallace-Tree adders, each Wallace-Tree adder for summing binary data bits from one or more columns and generating a partial sum (74) and a partial carry (76). Each modified Wallace-Tree adder has a plurality of stages (70, 110, 130, 150) comprising one-bit (30) and two-bit (60) full adders for reducing the number of the binary data bits, the last stage (36, 122, 142, 162) comprising a single one-bit full adder (36, 122, 142, 162) for generating the partial sum (74) and the partial carry results (76). A plurality of conductors interconnects the stages of each modified Wallace-Tree adder with stages in the same Wallace-Tree adder and with stages in other modified Wallace-Tree adders.</p>
申请公布号 WO1995004964(A1) 申请公布日期 1995.02.16
申请号 US1994008714 申请日期 1994.08.01
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