A gate array LSI having functional blocks formed by interconnecting a plurality of basic cells (10) arranged on a semiconductor substrate in matrix form and either signal conductive patterns (7) or first power conductive patterns (5). The first power conductive patterns (5) are disposed on the plurality of basic cells (10) arranged in line and are divided and disposed on the basic cells so that the signal conductive pattern (7) is interposed therebetween. It is therefore possible to improve the efficiency of wiring macrocells. <IMAGE>
申请公布号
EP0638936(A1)
申请公布日期
1995.02.15
申请号
EP19940305794
申请日期
1994.08.04
申请人
OKI ELECTRIC INDUSTRY COMPANY, LIMITED
发明人
INOUE, TORU, C/O OKI ELECTRIC IND. CO. LTD.;AMIYA, MICHIHIRO, C/O OKI ELECTRIC IND. CO. LTD.;TAKAHASHI, TADAO, C/O OKI ELECTRIC IND. CO. LTD.