发明名称 INTEGRAL DELAY LOCK LOOP
摘要 PURPOSE:To miniaturize hardware and to reduce the degradation in performance due to the change of circumstances, miniaturization of a device, crowdedness of circuit constituting elements, or the like by applying the output of a specific voltage adder as a control voltage to a voltage controlled clock generator and holding the synchronism based on the integral result of a specific integrator. CONSTITUTION:The output voltage of a reference voltage generator 5 and the sine wave voltage of an oscillator 6 are added by a voltage adder 7, and the result is supplied as the control voltage of a voltage controlled clock generator VCO 4. The output clock of this VCO 4 is used to generate a spread code in a spread code generator PN.GEN 1 in a receiver. Correlations between the spread code generated by the PN.GEN 1 and that of the reception signal are taken by a correlator 2, and the output of the correlator 2 has the DC component cut by a DC cut capacitor 3 and is supplied to an integrator 8. Simultaneously, a digital clock 20 obtained by digitizing the output of an oscillator 6 by a comparator 9 is supplied to the integrator 8 also. The output of this integrator 8 is supplied to the adder 7 to simplify the circuit.
申请公布号 JPH0746156(A) 申请公布日期 1995.02.14
申请号 JP19930189814 申请日期 1993.07.30
申请人 MITSUBISHI ELECTRIC CORP 发明人 KAWANAMI MASASHI
分类号 H04B1/707;H04B1/7085;H04L7/00;H04L7/033 主分类号 H04B1/707
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