| 摘要 |
A p-type pillared layer, made of a silicon single crystal, is formed on a bit line formed of an n-type diffusion layer by expitaxial growth. An FET, in which a gate electrode is provided through an insulating film and a side surface of the pillared layer is served as a channel area, is formed around the pillared layer. Also, a lower electrode, formed of an n-type silicon layer contacting an upper portion of the pillared layer, an insulating film, and an upper electrode are sequentially provided to surround the FET, thereby constituting a capacitor. The receptive elements are overlaid on each other in a vertical direction, so that a processing margin becomes zero and the wire connecting the respective elements is omitted, and a degree of integration of a semiconductor memory can be improved.
|
