| 摘要 |
<p>PURPOSE:To simplify data exchanging processing among a master CPU and N slave CPUs. CONSTITUTION:The master CPU (M) 1 manages N slave CPUs 2-1 to 2-N and optionally fetches data from respective slave CPUs 2-1 to 2-N to process them. The master CPU (M) 1 outputs a CPU hold signal (slave CPU stop signal) to an optional slave CPU, e.g. the slave CPU 2-1, and after stopping the CPU 2-1, switches a dual port memory 5 to the bus 8 side and fetches data. After fetching the data, the memory 5 is switched to the CPU (S) 3 side and the CPU hold signal is reset, so that the slave CPU 2-1 starts its operation and is returned to its normal state.</p> |
