发明名称 BIT SERIAL DIGITAL SIGNAL PROCESSOR
摘要 PURPOSE:To attain the reduction (so called, down-sizing) of the circuit scale of a bit serial digital signal processor in which orthogonal transformation such as discrete cosine transformation or each kind of digital signal processing can be executed by a bit serial arithmetic operation. CONSTITUTION:Forward disk cosine transformation is operated to input signals f0, f1,...f7 by a bit serial arithmetic operation, and output signals F0, F1,...F7 are obtained. The parts denoted by F in the flip flops are intrinsic circuit parts which are not used at the time of inverse discrete cosine transformation. Orthogonality at each stage sometimes disappears at the time when derived from a prototype (basic) signal flow. However, circuit blocks having orthogonality can still exist if one specifies the circuit blocks without paying attention to the stage.
申请公布号 JPH0722959(A) 申请公布日期 1995.01.24
申请号 JP19940058263 申请日期 1994.03.04
申请人 CASIO COMPUT CO LTD 发明人 WATANABE TORU
分类号 H03M7/30;G06F17/14;G06T9/00;H04N1/41;H04N19/42;H04N19/423;H04N19/436;H04N19/60;H04N19/625;H04N19/85;H04N19/91 主分类号 H03M7/30
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