发明名称 |
Semiconductor memory device |
摘要 |
A non-volatile memory element comprising a control gate formed by a diffusion layer, a floating gate comprising a conductive layer, the floating gate being partly overlapping with the control gate through a thin insulating layer, and a barrier layer formed to cover a part or the entire part of the floating gate is used as a defect remedy circuit for the memory circuit having read-only memory elements arranged in the form of a matrix for storing defective addresses corresponding to the word lines and bit lines and storing data corresponding thereto respectively.
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申请公布号 |
US5383162(A) |
申请公布日期 |
1995.01.17 |
申请号 |
US19920935176 |
申请日期 |
1992.08.26 |
申请人 |
HITACHI, LTD.;HITACHI VLSI ENGINEERING CORP. |
发明人 |
SHIRAI, MASAKI;MORIUCHI, HISAHIRO;YOSHII, YASUHIRO;KURODA, KENICHI;MATSUO, AKINORI |
分类号 |
G11C29/00;H01L27/112;H01L27/115;(IPC1-7):H01L27/10;G11C11/40 |
主分类号 |
G11C29/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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