发明名称 PHASE LOCK LOOP CIRCUIT
摘要 PURPOSE:To suppress jitter and noise sneaked into a power supply by constituting logic circuits for a phase comparator circuit in a PLL circuit of the current constant logic elements so as to supply a fixed bias current to all current constant logic elements. CONSTITUTION:This phase comparator circuit consists of a logic circuit 11 constituted of plural current constant logic elements and a bias circuit 12 for converting information detected by the circuit 11 into voltage. Voltage VP in the circuit 11 to be a fixed bias voltage for the current constant logic elements is supplied from the circuit 12 to all the current constant logic elements. Since the phase comparator circuit in the phase lock loop(PLL) circuit is constituted of plural current constant logic elements and the fixed bias current is supplied to the logic elements, a through current can be fixed in any of the steady state and transition state of the logic circuit 11.
申请公布号 JPH077420(A) 申请公布日期 1995.01.10
申请号 JP19920302239 申请日期 1992.11.12
申请人 ASAHI KASEI MICRO SYST KK 发明人 KUNISHI MASATOSHI
分类号 H03K5/26;H03K3/0231;H03K17/16;H03K19/017;H03L7/085;H03L7/089;H03L7/099 主分类号 H03K5/26
代理机构 代理人
主权项
地址